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Wspi0m0-rx { Wspi0m0-cs1 { Wspi0-1spi0m1-clk {Wspi0m1-cs0 {Wspi0m1-tx {Wspi0m1-rx {Wspi0m1-cs1 {Wspi0-2spi0m2-clk {W.spi0m2-cs0 {W1spi0m2-tx {W/spi0m2-rx {W0i2s1i2s1-mclk {Ui2s1-sclk {Ui2s1-lrckrx {Ui2s1-lrcktx {Ui2s1-sdi {Ui2s1-sdo {Ui2s1-sdio1 {Ui2s1-sdio2 {Ui2s1-sdio3 {Ui2s1-sleep� {VVVVVVVVVi2s2-0i2s2m0-mclk {Ui2s2m0-sclk {Ui2s2m0-lrckrx {Ui2s2m0-lrcktx {Ui2s2m0-sdi {Ui2s2m0-sdo {Ui2s2m0-sleep` {VVVVVVi2s2-1i2s2m1-mclk {Ui2s2m1-sclk {Ui2sm1-lrckrx {Ui2s2m1-lrcktx {Ui2s2m1-sdi {Ui2s2m1-sdo {Ui2s2m1-sleepP {VVVVVspdif-0spdifm0-tx {Uspdif-1spdifm1-tx {Uspdif-2spdifm2-tx {Usdmmc0-0sdmmc0m0-pwren {Xsdmmc0m0-pin {Xsdmmc0-1sdmmc0m1-pwren {Xsdmmc0m1-pin {Xgsdmmc0sdmmc0-clk {YGsdmmc0-cmd {ZHsdmmc0-dectn {XIsdmmc0-wrprt {Xsdmmc0-bus1 {Zsdmmc0-bus4@ {ZZZZJsdmmc0-pins� {XXXXXXXXsdmmc0extsdmmc0ext-clk {[sdmmc0ext-cmd {Xsdmmc0ext-wrprt {Xsdmmc0ext-dectn {Xsdmmc0ext-bus1 {Xsdmmc0ext-bus4@ {XXXXsdmmc0ext-pins� {XXXXXXXXsdmmc1sdmmc1-clk { Ysdmmc1-cmd { Zsdmmc1-pwren {Zsdmmc1-wrprt {Zsdmmc1-dectn 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�voltage ��w@2Z� sdmmc-regulatorregulator-fixed a�g�defaultvcc_sd8J2Z�b2Z� Kvdd-5vregulator-fixedvdd_5v$8JLK@bLK@+vdd-5v-lanregulator-fixed � e�h�default vdd_5v_lan$8 + compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio